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- 5-bit parallel-In/parallel-out shift register asynchronous preset
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- 4-bit shift register, parallel In, parallel out, serial input
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- 4-bit shift register, dual asynchronous presets
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- 4-bit binary counter separate divide-by-2 and divide-by-8 sections
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- divide-by-12 counter separate divide-by-2 and divide-by-6 sections
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- 8-bit shift register, serial In, serial out, gated input
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- Decade and Binary Counters
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- Quad 2-Input Exclusive-OR Gate
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- 4-bit magnitude comparator
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- 4-bit binary full adder
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- dual negative edge triggered J-K flip-flop with preset, common clock, and common clear
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- Dual J-K Flip-Flops with preset and clear function
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- 4-bit bistable latch
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- Dual D-type Positive Edge-triggered Flip-Flops
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- dual D positive edge triggered flip-flop with preset and clear
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- dual J-K flip-flop with clear
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- 8-bit equality comparator
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- 4 x 4 Register File With 3-State Outputs The TTL
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- octal bus transceiver
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- 8-bit shift registers with output latches three-state parallel outputs
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- octal D-type edge-triggered flip-flop with three-state outputs
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- octal D-type transparent latch with three-state outputs
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2-Wide 4-Input AND-OR-INVERT Gate
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- non-inverting octal buffer with three-state outputs
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- inverting octal buffer with three-state outputs
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- Two 2-input and Two 3-input AND-OR-INVERT Gate
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- expandable 4-wide 2-input AND-OR-invert gate
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- Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gate
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- BCD to 7-Segment Decoder
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- BCD to 7-segment decoder/driver with 15 V open collector outputs
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