74HC112 DIP IC Dual J K Flip Flop With Set And Reset Negative Edge Trigger (74HC112 IC)

The 74HC112 is a dual J K flip flop integrated circuit designed for storing and controlling digital data in sequential logic systems. Each flip flop changes state based on the J and K inputs and is triggered on the negative edge of the clock signal allowing controlled data storage and toggle operations.

This IC belongs to the high speed CMOS logic family and provides reliable switching performance with low power consumption. It includes asynchronous set and reset inputs which allow direct control of the output states making it suitable for counters registers and control logic circuits. The DIP package allows easy integration into breadboard prototypes and PCB based circuit designs.

Key Features

• Dual J K flip flops
• Negative edge triggered clock operation
• Asynchronous set and reset inputs
• High speed CMOS logic family
• Low power consumption with reliable switching
• Suitable for counters registers and sequential logic circuits
• DIP package suitable for prototyping and PCB mounting

Specifications

• IC Model = 74HC112
• Logic Type = Dual J K flip flop
• Trigger Type = Negative edge triggered
• Logic Family = HC CMOS
• Package Type = DIP
• Pin Count = 16
• Operating Voltage = 2V to 6V

Interfaces

• J1 = J input flip flop 1
• K1 = K input flip flop 1
• CLK1 = Clock input flip flop 1
• SET1 = Set input flip flop 1
• RESET1 = Reset input flip flop 1
• Q1 = Output flip flop 1
• Q1BAR = Inverted output flip flop 1
• J2 = J input flip flop 2
• K2 = K input flip flop 2
• CLK2 = Clock input flip flop 2
• SET2 = Set input flip flop 2
• RESET2 = Reset input flip flop 2
• Q2 = Output flip flop 2
• Q2BAR = Inverted output flip flop 2
• VCC = Power supply
• GND = Ground