74LS138 DIP 3 to 8-line Decoder/Demultiplexer
The 74LS138 is a high speed TTL integrated circuit designed for high performance memory-decoding or data-routing applications requiring very short propagation delay times. This device accepts three binary weighted inputs and when enabled provides eight mutually exclusive active low outputs. It features three enable inputs, two active low and one active high, which reduce the need for external gates or inverters when expanding to larger decoders.
This IC can be used as an 8-output demultiplexer by using one of the active low enable inputs as the data input and the other enable inputs as strobes. The 74LS138 is ideal for high speed address decoding in microprocessor systems or for complex routing in digital communication. Its low power Schottky technology ensures minimal power consumption while providing the fast switching speeds necessary for modern computing architectures.
KEY FEATURES
- 3-line to 8-line decoding capability
- Multiple enable inputs for easy expansion and cascading
- Active low outputs for direct interface with system buses
- Functions as a demultiplexer for data distribution
- Low power Schottky design for high speed efficiency
- Standard 16 pin dual in line package
SPECIFICATIONS
- Supply Voltage 4.75V to 5.25V
- Operating Temperature 0 to 70 Celsius
- Logic Type TTL Low Power Schottky
- Propagation Delay 20ns
- High Level Output Current -0.4mA
- Low Level Output Current 8mA
- Input Voltage High 2.0V Minimum
INTERFACES
- A Address input A
- B Address input B
- C Address input C
- G1 Enable input 1 active high
- G2A Enable input 2A active low
- G2B Enable input 2B active low
- Y0 Output 0 active low
- Y1 Output 1 active low
- Y2 Output 2 active low
- Y3 Output 3 active low
- Y4 Output 4 active low
- Y5 Output 5 active low
- Y6 Output 6 active low
- Y7 Output 7 active low
- VCC Positive supply voltage
- GND Ground reference
