74LS155 DIP Dual 2-Line to 4-Line Decoder/Demultiplexer

The 74LS155 is a high speed TTL integrated circuit containing two independent 2-line to 4-line decoders in a single package. This device is designed with a unique architecture that allows the two sections to be used as either two separate decoders or combined into a single 3-line to 8-line decoder. Each section features its own set of four active low outputs and dedicated enable/data inputs.

This IC is highly versatile in digital systems for address decoding and data distribution. One section uses an active high data input while the other uses an active low data input, which simplifies the process of cascading the device to form larger decoding arrays. The low power Schottky technology ensures that the decoding and demultiplexing operations occur with high speed and low power consumption, making it suitable for memory management and peripheral control.

KEY FEATURES

• Dual independent 2-line to 4-line decoders
• Can be cascaded to function as a 3-line to 8-line decoder
• Active low outputs for direct system bus compatibility
• Individual data and strobe inputs for each section
• Low power Schottky design for high speed efficiency
• Standard 16 pin dual in line package

SPECIFICATIONS

• Supply Voltage 4.75V to 5.25V
• Operating Temperature 0 to 70 Celsius
• Logic Type TTL Low Power Schottky
• Typical Propagation Delay 18ns
• High Level Output Current -0.4mA
• Low Level Output Current 8mA
• Input Voltage High 2.0V Minimum

INTERFACES

• A Address input A common
• B Address input B common
• 1C Decoder 1 data input active low
• 1G Decoder 1 strobe input active low
• 1Y0 to 1Y3 Decoder 1 outputs 0 through 3 active low
• 2C Decoder 2 data input active high
• 2G Decoder 2 strobe input active low
• 2Y0 to 2Y3 Decoder 2 outputs 0 through 3 active low
• VCC Positive supply voltage
• GND Ground reference