74LS173 DIP Quad D-Type Flip-Flop With Three-State Outputs
The 74LS173 is a high speed TTL integrated circuit containing four D-type flip-flops with 3-state outputs. This device is designed specifically for use in bus-oriented systems where multiple outputs need to be connected to a common data bus. The outputs can be placed in a high-impedance state, effectively disconnecting them from the bus, which allows for efficient data multiplexing and memory-mapped I/O operations without the need for additional logic gates.
The flip-flops are edge-triggered and store the information present at the D inputs on the positive-going transition of the clock. A unique feature of the 74LS173 is the dual data-enable inputs, which must both be low for the device to accept new data. This provides a secondary layer of control, ensuring that data is only loaded when specific system conditions are met. An asynchronous master reset is also included, which immediately clears all flip-flops to a low state regardless of the clock or enable inputs.
KEY FEATURES
- Quad D-type flip-flops in a single package
- 3-state outputs for direct connection to system buses
- Gated data-enable inputs for precise loading control
- Asynchronous master reset for immediate system clearing
- Low power Schottky technology for high speed and efficiency
- Standard 16 pin dual in line package
SPECIFICATIONS
- Supply Voltage 4.75V to 5.25V
- Operating Temperature 0 to 70 Celsius
- Logic Type TTL Low Power Schottky
- Maximum Clock Frequency 30MHz
- Typical Propagation Delay 18ns
- High Level Output Current -2.6mA
- Low Level Output Current 24mA
INTERFACES
- D1 to D4 Data inputs
- G1 G2 Data enable inputs active low
- CLK Clock input positive edge triggered
- MR Master reset active asynchronous
- M N Output enable inputs active low
- Q1 to Q4 3-state parallel outputs
- VCC Positive supply voltage
- GND Ground reference
