74LS180 DIP 9-Bit Odd/Even Parity Bit Generator and Checker
The 74LS180 is a high speed TTL integrated circuit designed to perform parity generation and checking for 8-bit data words plus a ninth parity bit. It features eight data inputs and two control inputs labeled "Even" and "Odd." This device is essential for error detection in digital communication systems, where it can verify the integrity of data transmitted over serial or parallel buses.
The circuit provides two outputs, "Sum Even" and "Sum Odd," which indicate the parity of the input data based on the logic levels applied to the control inputs. This architecture allows the 74LS180 to be easily expanded to handle any number of bits by cascading multiple units together. Its low power Schottky technology ensures that parity calculations are performed with minimal propagation delay, maintaining high system throughput in data-intensive applications.
KEY FEATURES
- 9-bit parity generation and checking capability
- Independent Even and Odd control inputs
- Dual outputs for Sum Even and Sum Odd logic
- Easily cascadable for word lengths greater than 9 bits
- Low power Schottky technology for high speed operation
- Standard 14 pin dual in line package
SPECIFICATIONS
- Supply Voltage 4.75V to 5.25V
- Operating Temperature 0 to 70 Celsius
- Logic Type TTL Low Power Schottky
- Typical Propagation Delay 33ns
- High Level Output Current -0.4mA
- Low Level Output Current 8mA
- Input Voltage High 2.0V Minimum
INTERFACES
- A to H 8-bit data inputs
- EVEN Parity control input even
- ODD Parity control input odd
- SUM EVEN Parity output even
- SUM ODD Parity output odd
- VCC Positive supply voltage
- GND Ground reference
