74LS78 DIP Dual Negative Edge Triggered J K Flip Flop With Preset Common Clock And Common Clear

The 74LS78 DIP is a TTL logic integrated circuit that contains two negative edge triggered J K flip flops with asynchronous preset and common clear inputs in a 14 pin dual inline package. It belongs to the 74LS low power Schottky logic family and is designed for sequential logic and timing applications.

Both flip flops share a common clock and common clear input, making it suitable for synchronized control operations in counters, frequency dividers, and digital state machines. The negative edge triggering ensures state change occurs on the falling edge of the clock signal.

KEY FEATURES

• Dual J K flip flop configuration
• Negative edge triggered operation
• Asynchronous preset inputs
• Common clock input
• Common clear input
• TTL compatible logic levels
• DIP 14 pin package

SPECIFICATIONS

• IC Model 74LS78
• Logic Function Dual negative edge triggered J K flip flop
• Package Type DIP 14
• Logic Family 74LS TTL
• Operating Voltage 5V DC
• Trigger Type Negative edge triggered
• Preset Type Asynchronous preset
• Clear Type Asynchronous common clear
• Operating Temperature Standard commercial range

INTERFACES



• Common clock input
• Common clear input
• Preset 1 input
• J1 input
• K1 input
• Q1 output
• Q1 complement output
• Preset 2 input
• J2 input
• K2 input
• Q2 output
• Q2 complement output
• GND Ground
• VCC 5V power supply